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this is information on a product in full production. november 2014 docid026845 rev 1 1/12 ESDAXLC6-1BT2Y automotive single-line extra low capacitance transil?, transient surge voltage suppressor (tvs) for esd protection datasheet ? production data features ? single-line bidirectional protection ? breakdown voltage = 6 v min. ? extra low diode capacitance = 0.4 pf ? lead-free package ? ecopack ? 2 compliant ? aec-q101 qualified benefits ? low capacitance for optimized data integrity ? low leakage current < 50 na ? low pcb space consumption: 0.6 mm 2 complies with the following standards: ? iec 61000-4-2 (exceeds level 4) ? 30 kv (air discharge) ? 16 kv (contact discharge) ? iso10605: c = 330 pf, r = 330 ? ? 30 kv (air discharge) ? 12 kv (contact discharge) ? iso 7637-3: ? pulse 3a: v s = -150 v ? pulse 3b: v s = +100 v applications where transient overvoltage protection in esd sensitive equipment is required, such as: ? automotive applications ? computers ? printers ? communication systems ? cellular phone handsets and accessories ? video equipment description the ESDAXLC6-1BT2Y is bidirectional single-line tvs diode designed to protect data lines or other i/o ports against esd transients. this device is ideal for applications where both reduced line capacitance and power absorption capability are required. figure 1. functional diagram tm : transil is a trademark of stmicroelectronics 62'7 3lq 3lq www.st.com
characteristics ESDAXLC6-1BT2Y 2/12 docid026845 rev 1 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp electrostatic discharge capability iec 61000-4-2 : contact discharge air discharge 16 30 kv iso 10605 - c = 330 pf, r = 330 ? : contact discharge air discharge 12 30 mil std 883g - method 3015-7: class3 25 p pp peak pulse power dissipation (8/20 s) t j initial = t amb 40 w i pp peak pulse current (8/20 s) 1.3 a t j operating junction temperature range - 55 to + 150 c t stg storage temperature range - 65 to + 150 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics (values, t amb = 25 c) symbol test condition min. typ. max. unit v br i r = 1 ma 6 9 11 v i rm v rm = 3 v 50 na r d dynamic resistance, pulse width 100 ns 0.25 ? v cl 8 kv contact discharge after 30 ns iec 61000-4-2 37 v c line f = (200 mhz - 3000 mhz), v r = 0 v 0.4 0.5 pf symbol parameter v = breakdown voltage i = leakage current @ v v = stand-off voltage i = peak pulse current c = parasite capacitance r br rm rm rm pp d = dynamic impedance t = voltage temperature coefficient
docid026845 rev 1 3/12 ESDAXLC6-1BT2Y characteristics 12 figure 3. junction capacitance versus reverse voltage applied (typical values) figure 4. leakage current versus junction temperature (typical values) $ q'
9 5 9 7m?& , 5 q$ figure 5. s21 attenuation measurement figure 6. tlp measurements 0 0 * * * * 6g% )+] , 33 $ 9 &/ 9
characteristics ESDAXLC6-1BT2Y 4/12 docid026845 rev 1 figure 7. esd response to iso 10605, c = 150 pf, r = 330 ? (+8 kv contact) figure 8. esd response to iso 10605, c = 150 pf, r = 330 ? (-8 kv contact) otejw 7ejw otejw 7ejw figure 9. response to iso 7637-3 (pulse 3a) u s = -150 v figure 10. response to iso 7637-3 (pulse 3b) u s = +100 v 9gly p$gly qvgly 9gly p$gly qvgly
docid026845 rev 1 5/12 ESDAXLC6-1BT2Y package information 12 2 package information ? epoxy meets ul94, v0 ? lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 11. sod882t dimension definitions pin # 1 id e d a1 a l1 e l2 b2 b1
package information ESDAXLC6-1BT2Y 6/12 docid026845 rev 1 note: product marking may be rotated by multiples of 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. table 3. sod882t dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.30 0.40 0.012 0.016 a1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 d 0.55 0.60 0.65 0.022 0.024 0.026 e 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 l1 0.20 0.25 0.30 0.008 0.010 0.012 l2 0.20 0.25 0.30 0.008 0.010 0.012 figure 12. sod882t footprint in mm (inches) figure 13. sod882t marking 0.55 (0.022) 0.40 (0.016) 0.50 () 0.020 0.55 (0.022) 3lq 3lq 8
docid026845 rev 1 7/12 ESDAXLC6-1BT2Y package information 12 figure 14. sod882t tape and reel specifications %dulqglfdwhv3lq 8vh ugluhf wlrq rixq uhh olqj $oo glphqvlrqvduhlqpp ? ? ? ? ? ?? ? ? ? ? 8 8 8 8 8 8
recommendation on pcb assembly ESDAXLC6-1BT2Y 8/12 docid026845 rev 1 3 recommendation on pcb assembly 3.1 stencil opening design 1. general recommendation on stencil opening design a) stencil opening dimensions: l (length), w (width), t (thickness). figure 15. stencil opening dimensions b) general design rule stencil thickness (t) = 75 ~ 125 m 2. reference design a) stencil opening thickness: 100 m b) stencil opening for central exposed pad: opening to footprint ratio is 50%. c) stencil opening for leads: opening to footprint ratio is 90%. figure 16. recommended stencil window position in mm (inches) l t w aspect ratio w t ----- 1.5 = aspect area lw 2t l w + () --------------------------- - 0.66 = lead footprint on pcb stencil window opening 0.55 (0.022) 0.50 (0.020) 0.40 (0.016) 0.522 (0.021) 0.474 (0.019) 0.014 (0.00055) 0.014 (0.00055) 0.013 (0.00051) 0.013 (0.00051)
docid026845 rev 1 9/12 ESDAXLC6-1BT2Y recommendation on pcb assembly 12 3.2 solder paste 1. halide-free flux qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20-45 m. 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead rec ognition capabilities of th e placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks a nd open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
recommendation on pcb assembly ESDAXLC6-1BT2Y 10/12 docid026845 rev 1 3.5 reflow profile figure 17. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. maximum soldering profile corresponds to the latest ipc/jedec j-std-020. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
docid026845 rev 1 11/12 ESDAXLC6-1BT2Y ordering information 12 4 ordering information figure 18. ordering information scheme 5 revision history table 4. ordering information order code marking (1) 1. the marking can be rotated by multiples of 90 to differentiate assembly location package weight base qty delivery mode ESDAXLC6-1BT2Y u sod882t 0.80 mg 12000 tape and reel (6'$;/& %7< (6'duud\ ([wudorzfdsdflwdqfh %uhdngrzqyrowdjh 9rowvplq 1xpehuriolqhv 'luhfwlrqdo % %lgluhfwlrqdo 3dfndjh 7 7klq62' $xwrprwlyh table 5. document revision history date revision changes 03-nov-2014 1 initial release.
ESDAXLC6-1BT2Y 12/12 docid026845 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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